The memory controller chip

A physical address is used by the CPU to access information that is stored in the memory. Yet, the CPU does not directly handle this process; but, instead, turns it over to the memory controller chip, also known as the MCC.

The MCC contains the logic for reading and writing of data to the computer’s main memory (DRAM). Earlier designs placed the MCC [on the motherboard] within a chip, called the northbridge; but, currently, this chip is also integrated into the CPU. This new design has greatly decrease memory latency. But as a consequence of the integration, CPUs are now limited to only one specific type of memory.

The address and external data bus connect the memory controller to the CPU. When information is needed, the CPU sends a request to the MCC; this request contains the location (address) of the needed information that is currently being stored within the RAM. The MCC, which is also connected to the RAM by a multiplexer (combination of both a multiplexer and a demultiplexer), locates the information and sends it back to the CPU.

The responsibilities of the memory controller extend beyond the reading and writing of data. For instance, it can also assist in maintaining the RAM storing capabilities — RAM [in general], is volatile  —meaning, it needs to be constantly refreshed with power to preserve data. The memory controller regulates this power refreshment.

Some memory controllers use a technique, called memory scrambling; here the user’s information is scrambled before it is sent to the RAM. This helps to prevent cold boot attacks, where sensitive information can be directly accessed from the memory modules.   

Flash memory, which is a hybrid of RAM and ROM, also has a memory controller. But, unlike RAM, flash memory does not require power to retain its data. Therefore, its memory controller only reads and writes information.  

So, the memory controller plays the role of the middleman for the CPU and the computer’s main memory. It takes on some of the responsibilities that would have, otherwise, been left up to the CPU.

Leave a Reply

Your email address will not be published. Required fields are marked *